1. Field of the Invention
The present invention is related to semiconductor memory devices, and more particularly to the test and characterization of static memory cells and related interface circuits.
2. Description of the Related Art
A memory array which is fabricated in an integrated circuit may be functionally tested using a variety of well known algorithms. These tests may be conducted to provide thorough test coverage under margined operating conditions, and memory arrays having one or more failing memory cells may be rejected (or alternatively, replaced by a redundant memory element). Unfortunately, it is frequently very difficult to determine the cause of a failing memory cell, a failing column, or a failing row within the memory array, especially if the memory array is embedded within a large integrated circuit such as a microprocessor.
Various methods have been used to try to detect the underlying causes of failing memory arrays, as well as to determine the operating margins of the memory array. Many methods require significant inferences to be drawn, based on a series of test results using a variety of test patterns and operating conditions. But without direct access to internal circuit nodes, frequently such inferences are inconclusive. Microprobing has been used to afford access to internal bit lines and word lines of a memory array, but this is a difficult and very time consuming procedure, and even more so at environmental extremes. Moreover, as line widths have become smaller, and as additional layers of metal interconnect frequently overlay the nodes of interest, microprobing has effectively lost much of its previous viability as a diagnostic and characterization tool.
Nonetheless, larger and larger memory arrays are being integrated into a variety of integrated circuits. In many such circuits, over half of the transistors used in the circuit are used to implement the memory array. Characterization of the memory array is therefore increasingly important. Improved methods are needed, especially for those memory arrays which may be incorporated or embedded within large, sophisticated integrated circuits such as microprocessors.
The stability of both resistor-load and full CMOS (PMOS loads) SRAM memory cells is investigated, and expressions for static noise margin derived, in Seevinck, et al., "Static-Noise Margin Analysis of MOS SRAM Cells," IEEE Journal of Solid-State Circuits, Vol. SC-22, No. 5, pp. 748-54 (October, 1987).
A systematic approach for failure analysis for yield enhancement and reliability improvement for BiCMOS SRAM memory cells is described in Hall, et al., "A Structured Approach for Failure Analysis of a 256K BiCMOS SRAM," Conference Proceedings of The Failure Analysis Forum for Microelectronics and Advanced Materials, pp. 167-76 (November, 1989).